Accumulator & Decoders
Sequential accumulator loop with magnitude comparators & decoder trees.
RISC-V 32-bit ALU
32-bit arithmetic operations, SLT logic, and Zero branch condition flag.
4-State Sequence Detector
Mealy/Moore FSM state transitions & synchronous registered registers.
Synchronous FIFO Buffer
Dual circular pointers with memory registers and full/empty flags.
✨ Blank HDL Module
Clear the workspace and write your own SystemVerilog from scratch.